See also:State transition logic for this FSM
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.
一种写法
module top_module(input clk,input in,input areset,output out); //parameter A = 2'b00,B = 2'b01,C = 2'b11,D = 2'b10;reg [1:0] state;reg [1:0] next_state;// State transition logicalways@ (*) begincase(state)A:if(in == 1)next_state <= B;elsenext_state <= A;B:if(in == 0)next_state <= C;elsenext_state <= B;C:if(in == 1)next_state <= D;elsenext_state <= A;D:if(in == 1)next_state <= B;elsenext_state <= C;default: next_state <= A;endcaseend// State flip-flops with asynchronous resetalways@(posedge clk or posedge areset)if(areset)state <= A;elsestatemodule top_module(input clk,input in,input areset,output out); //parameter A = 2'b00,B = 2'b01,C = 2'b11,D = 2'b10;reg [1:0] state;reg [1:0] next_state;// State transition logicalways@ (*) beginstate<= next_state;end // State flip-flops with asynchronous resetalways@(posedge clk or posedge areset)if(areset)next_state <= A;else case(next_state)A:if(in == 1)next_state <= B;elsenext_state <= A;B:if(in == 0)next_state <= C;elsenext_state <= B;C:if(in == 1)next_state <= D;elsenext_state <= A;D:if(in == 1)next_state <= B;elsenext_state <= C;default: next_state <= A;endcase // Output logicassign out = state == D ? 1'b1 : 1'b0;endmodule